A seven segment display is seven individually controllable LED segments, labelled a through g, arranged to form the shape of a digit, plus usually one more LED for a decimal point. Driving one from an FPGA means outputting a 7-bit pattern, one bit per segment, that lights the correct combination of segments to show a given digit, 0 through 9.
In a common cathode display, all seven segment cathodes share a common ground pin, and each segment lights when its individual pin is driven to logic HIGH (1). In a common anode display, all seven segment anodes share a common supply pin, and each segment lights when its individual pin is driven to logic LOW (0). This single detail, which type of display you have, determines whether every segment pattern in this guide needs to be used as written or inverted, and it is the one thing worth confirming before touching a breadboard.
Quick reference:
| Parameter | Specification |
|---|---|
| Segments | 7 (labelled a through g) plus optional decimal point |
| Common cathode | Segment ON when driven HIGH (1) |
| Common anode | Segment ON when driven LOW (0) |
| FPGA output | 7-bit (or 8-bit with decimal point) pattern per digit |
| Typical series resistor | 220–330 ohm per segment |
What Most Beginners Get Wrong
Most beginners wire up a seven segment display, load a pattern that is supposed to show the digit 3, and instead get a scrambled, half-lit mess or nothing at all. The most common cause is not a wiring mistake but a polarity mistake: assuming the display is common cathode when it is actually common anode, or the reverse. On a common cathode display, all the segment cathodes are tied together to ground, and each segment lights when its anode pin is driven HIGH. On a common anode display, all the segment anodes are tied together to the supply voltage, and each segment lights when its cathode pin is driven LOW, the inverse logic. The segment patterns you write in Verilog are exact opposites between the two types, so identifying which one you have, usually printed on the datasheet or checked with a multimeter’s diode-test mode, is the first step, not an afterthought.
Seven Segment Display Pinout
A standard single-digit seven segment display has 10 pins: one pin per segment (a, b, c, d, e, f, g), one pin for the decimal point (dp), and two common pins (tied together internally, either both cathode or both anode, so only one needs to be connected). The segment layout follows a consistent naming convention across manufacturers:
aaa
f b
f b
ggg
e c
e c
ddd dp
Segment a is the top bar, b and c are the right side top and bottom, d is the bottom bar, e and f are the left side bottom and top, and g is the middle bar. This layout is what every digit pattern below is built from.
Segment Patterns for Each Digit
Each digit is a specific combination of lit segments. The table below gives the pattern for a common cathode display, where 1 means the segment is on. For a common anode display, invert every bit (0 becomes on, 1 becomes off).
| Digit | a | b | c | d | e | f | g |
|---|---|---|---|---|---|---|---|
| 0 | 1 | 1 | 1 | 1 | 1 | 1 | 0 |
| 1 | 0 | 1 | 1 | 0 | 0 | 0 | 0 |
| 2 | 1 | 1 | 0 | 1 | 1 | 0 | 1 |
| 3 | 1 | 1 | 1 | 1 | 0 | 0 | 1 |
| 4 | 0 | 1 | 1 | 0 | 0 | 1 | 1 |
| 5 | 1 | 0 | 1 | 1 | 0 | 1 | 1 |
| 6 | 1 | 0 | 1 | 1 | 1 | 1 | 1 |
| 7 | 1 | 1 | 1 | 0 | 0 | 0 | 0 |
| 8 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| 9 | 1 | 1 | 1 | 1 | 0 | 1 | 1 |
Driving a Seven Segment Display in Verilog
it a natural companion to the full adder covered elsewhere in this guide: both are combinational circuits built from a defined input-to-output mapping rather than stored state.
The output is a 7-bit vector, and getting the bit order right matters: this module packs it as segments = {g, f, e, d, c, b, a}, meaning segments[6] drives segment g and segments[0] drives segment a. Wire each bit to the wrong physical pin and every digit renders as an unreadable, scrambled pattern, a different symptom from the common-cathode/anode mismatch but just as common a beginner error.
module seven_seg_decoder (
input wire [3:0] digit,
output reg [6:0] segments // segments = {g,f,e,d,c,b,a}, segments[6]=g ... segments[0]=a
);
// Common cathode patterns: 1 = segment on
always @(*) begin
case (digit)
4'd0: segments = 7'b0111111;
4'd1: segments = 7'b0000110;
4'd2: segments = 7'b1011011;
4'd3: segments = 7'b1001111;
4'd4: segments = 7'b1100110;
4'd5: segments = 7'b1101101;
4'd6: segments = 7'b1111101;
4'd7: segments = 7'b0000111;
4'd8: segments = 7'b1111111;
4'd9: segments = 7'b1101111;
default: segments = 7'b0000000; // blank for invalid input
endcase
end
endmodule
This uses always @(*) with a case statement, not always @(posedge clk…), which keeps it purely combinational: the output updates immediately whenever digit changes, with no clock edge and no stored state. If your display is common anode instead of common cathode, invert the output with a single line: assign segments_out = ~segments; immediately after the decoder, rather than rewriting every pattern in the case statement.
Multi-Digit Displays and Multiplexing
A single seven segment display shows one digit. Most real projects need more than one digit, a two-digit counter or a four-digit clock, for example, and wiring a full 7 (or 8) segment lines per digit quickly uses more FPGA pins than are practical. The standard solution is multiplexing: connect all digits’ segment pins together in parallel, give each digit its own common pin, and rapidly switch which digit’s common pin is active while updating the segment pattern to match.
The refresh math is worth getting precise rather than rounding to “fast enough.” Persistence of vision needs each individual digit refreshed at roughly 60 to 100 Hz or faster to look continuously lit rather than flickering, and that number is per digit, not the total switching rate. For an N-digit display, the actual scan rate needed is N times the per-digit refresh rate. A 4-digit display refreshed at 100 Hz per digit needs a scan rate of 400 Hz cycling through the four digits. This requires a clock-driven counter to manage the cycling, which is the first place this guide’s combinational and sequential halves, this circuit and the flip-flops covered earlier, work together in the same design.
One wiring detail matters once you multiplex more than one digit: the shared common pins carry the combined current of every segment lit on that digit at once, not just one segment’s worth. Depending on your FPGA’s per-pin current rating, driving a multi-digit common pin directly from an FPGA I/O pin can exceed what the pin is rated for. Check your specific board’s I/O current limits before wiring a multi-digit display, and use an external transistor as a driver stage on each common pin if the display’s combined segment current is close to or above the pin’s rating.
From Simulation to Real Hardware
On an EIM STEPFPGA board, connect the seven segment decoder’s outputs to the board’s onboard or externally wired seven segment display through the appropriate segment pins, with a series resistor per segment, typically in the 220 to 330 ohm range, to limit current and protect both the FPGA pins and the LEDs. Put one resistor on each of the seven segment lines, not a single resistor on the shared common pin: a single common resistor divides current differently depending on how many segments are lit at once, so digit 8 comes out dim and digit 1 comes out unusually bright, an inconsistent-brightness symptom that looks like a display fault but is actually a resistor placement mistake. Confirm common cathode versus common anode before wiring anything, since driving a common anode display with common cathode patterns lights every segment except the ones you intended, the exact scrambled-digit symptom covered above. Test with a fixed digit value first, 0 is easiest to visually confirm since it lights every segment except g, before connecting the decoder to a counter or any other changing input.
Where This Goes Next
This decoder is combinational, matching the full adder covered earlier in this guide, and it becomes especially useful once you have a value worth displaying: the output of a counter, or a chain of full adders doing real arithmetic. If you have not yet covered the sequential half of digital design, the flip-flops guide explains the memory elements a multi-digit multiplexed display’s cycling logic is built from.
For the complete build sequence, see FPGA Projects for Beginners. The FPGA Learning Kit includes a seven segment display and walks through this exact build.
Frequently Asked Questions
How do I know if my seven segment display is common cathode or common anode?
Check the datasheet first; it is usually stated directly. Without a datasheet, use a multimeter’s diode-test mode: touch the probes to a segment pin and a common pin. If a segment lights with the common pin on the black (negative) probe, the display is common cathode. If it lights with the common pin on the red (positive) probe, it is common anode.
Why does my seven segment display show the wrong digit or a scrambled pattern?
The most common cause is a common cathode versus common anode mismatch: the segment pattern you are sending assumes the opposite polarity from what the display actually is. Invert the output bits and retest before checking wiring.
How many pins does a seven segment display need on an FPGA?
A single digit needs 7 pins for the segments, plus 1 more if you are using the decimal point, so 7 or 8 total. A multi-digit multiplexed display adds one pin per additional digit for that digit’s common connection, but the segment pins stay shared across all digits.
Can a seven segment display show letters as well as numbers?
A limited set. Because only 7 segments are available, only some letters are recognizable: A, b, C, d, E, F, and a handful of others render clearly, while most letters cannot be represented accurately with 7 segments. This is a genuine hexadecimal-display limitation, not just a design choice, which is why 7-segment hex displays typically use a mix of uppercase and lowercase letterforms to stay legible.
Do I need a resistor for each segment?
Yes. Each segment is an individual LED, and driving it directly from an FPGA pin without a current-limiting resistor risks exceeding the LED’s or the FPGA pin’s maximum current rating. A series resistor per segment, sized for the display’s forward voltage and the FPGA’s output voltage, is standard practice, not optional.
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