Building a 1-Bit Full Adder with Verilog and FPGA

Introduction

Among all digital circuits, the adder stands out as one of the most essential building blocks. It performs arithmetic operations that underpin every modern computing and processing unit. In this article, we will focus on the simplest yet complete version: the 1-bit full adder. You will explore its logic principles, implement it in Verilog, map it onto an FPGA, and finally validate the design through hands-on experiments. This project is also featured in Chapter 3 of Fundamental Digital Circuits and FPGAs, where the full learning kit is available.

Understanding the Role of Adders in Digital Systems

A half adder is the simplest arithmetic circuit. It adds two binary digits (A and B) and produces a Sum and a Carry. Unlike decimal numbers where digits range from 0 to 9, binary arithmetic uses only 0 and 1, so even the simplest addition can generate a carry into the next higher bit.

However, in real systems, addition usually involves more than just two bits. That is where the full adder comes in. The full adder extends the logic by including a third input, called the carry-in (Cin). This allows multiple adders to be chained together, enabling multi-bit addition.

---

module full_adder(
    input wire a,
    input wire b,
    input wire cin,
    output wire sum,
    output wire co
);
    assign sum = a^b^cin;
    assign co = ((a^b)&cin)|(a&b);
endmodule

Input	Input	Input	Output	Output
CIN	A	B	Sum	COUT
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1