A full adder is a combinational digital circuit that adds three single-bit inputs, two operand bits (A, B) and a carry-in (Cin), and produces two outputs, a sum and a carry-out. Its Boolean equations are Sum = A XOR B XOR Cin and Cout = (A AND B) OR (Cin AND (A XOR B)). It has no memory and no clock: feed it inputs and the outputs settle almost instantly, which is what makes it combinational, not sequential. It is the building block every arithmetic circuit on an FPGA, from a counter’s increment logic to a full ALU, is made from.
Quick reference:
| Parameter | Specification |
|---|---|
| Inputs | A, B, Cin (3 single-bit) |
| Outputs | Sum, Cout (2 single-bit) |
| Sum equation | A XOR B XOR Cin |
| Cout equation | (A AND B) OR (Cin AND (A XOR B)) |
| Circuit type | Combinational (no clock, no memory) |
| Built from | 2 half adders + 1 OR gate |
Why a Full Adder Needs Three Inputs, Not Two
Most beginners jump straight to the full adder’s truth table and memorize eight rows without understanding why it needs three inputs instead of two. The answer is the carry. A single-bit adder that only takes two inputs, A and B, can produce a sum and a carry-out, but it has no way to accept a carry-in from a previous, less significant bit. Chain several of those together and the second bit has nowhere to put the carry it received from the first. The full adder exists specifically to solve that chaining problem, and understanding that reason makes the rest of this guide, particularly why it is built from two half adders, make sense instead of needing to be memorized.
The Half Adder: Adding Without a Carry-In
Before the full adder, there is a simpler circuit: the half adder. It adds exactly two single-bit inputs, A and B, with no carry-in, and produces a sum and a carry-out.
Half Adder truth table:
| A | B | Sum | Carry |
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 1 | 1 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
Boolean equations: Sum = A XOR B, Carry = A AND B
It is called a half adder because it does only half the job a real multi-bit addition needs: it produces a carry but cannot accept one. That is the exact gap the full adder closes.
The Full Adder: Closing the Gap
A full adder takes three inputs, A, B, and Cin (carry-in), and produces two outputs, Sum and Cout (carry-out). It can be built directly from two half adders and an OR gate, which is the cleanest way to see why its equations look the way they do.
Full Adder truth table:
| A | B | Cin | Sum | Cout |
|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 | 0 |
| 0 | 1 | 0 | 1 | 0 |
| 0 | 1 | 1 | 0 | 1 |
| 1 | 0 | 0 | 1 | 0 |
| 1 | 0 | 1 | 0 | 1 |
| 1 | 1 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 |
Boolean equations:
Sum = A XOR B XOR Cin
Cout = (A AND B) OR (Cin AND (A XOR B))
Building it from two half adders: the first half adder takes A and B, producing an intermediate sum and an intermediate carry (call it C1). The second half adder takes that intermediate sum and Cin, producing the final Sum and a second intermediate carry (C2). Cout is the OR of the two intermediate carries. Trace through the truth table with this structure in mind and every row follows directly from it, no memorization required.
Why OR and not something more complex for Cout? Because C1 and C2 can never both be 1 at the same time. If A and B alone produce a carry (C1 = 1), that means the intermediate sum going into the second half adder is 0, so C2 cannot also be 1. Since the two carries are mutually exclusive, a plain OR gate is enough to combine them correctly, no additional logic needed.
Chaining Full Adders: The Ripple Carry Adder
A single full adder adds one bit. Real arithmetic needs more than one bit. Chain multiple full adders together, feeding each one’s Cout into the next one’s Cin, and you get a ripple carry adder capable of adding numbers of any width, 4-bit, 8-bit, 32-bit, limited only by how many full adders you chain. Each bit position’s sum depends on the carry rippling in from the position before it, which is exactly what the carry-in input exists for.
This “ripple” is entirely a data-carry relationship between combinational adders, not a clock signal, and it is standard, correct design practice: the carry simply takes a fixed propagation delay to work its way from the least significant bit to the most significant one. That is worth stating plainly because it is easy to confuse with a different, genuinely bad practice that also uses the word “ripple”: a ripple counter, where flip-flops are clocked one from another’s output instead of from a shared clock. A ripple counter is a sequential, clock-routing problem, prone to glitches from accumulated clock skew. A ripple carry adder is a combinational, data-routing arrangement with no clock involved anywhere, and the two are unrelated beyond sharing a name.
Building a Full Adder in Verilog: Three Ways
There are three common styles for describing this circuit in Verilog, and seeing all three makes clear that Verilog does not care how you arrive at the same hardware.
Structural style, wiring gates directly, matching the two-half-adder diagram above:
module half_adder (
input wire a,
input wire b,
output wire sum,
output wire carry
);
assign sum = a ^ b;
assign carry = a & b;
endmodule
module full_adder_structural (
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire cout
);
wire sum1, carry1, carry2;
half_adder ha1 (.a(a), .b(b), .sum(sum1), .carry(carry1));
half_adder ha2 (.a(sum1), .b(cin), .sum(sum), .carry(carry2));
assign cout = carry1 | carry2;
endmodule
Behavioral style, describing the outputs directly from the Boolean equations, letting synthesis figure out the gates:
module full_adder_behavioral (
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire cout
);
assign sum = a ^ b ^ cin;
assign cout = (a & b) | (cin & (a ^ b));
endmodule
Both modules are combinational, note that neither uses always @(posedge clk…) or any clock at all, which is the Verilog signature of a circuit with no memory. Both synthesize to functionally identical hardware. The structural version is more code but mirrors the two-half-adder diagram directly, useful while you are still connecting the diagram to the syntax. The behavioral version is shorter and is what you will typically write once the underlying circuit is second nature, because letting synthesis choose the gate-level implementation from a correct Boolean equation is standard practice, not a shortcut that sacrifices anything.
Arithmetic style, the version most working engineers actually write, letting Verilog’s built-in addition operator do the job:
module full_adder_arithmetic (
input wire a,
input wire b,
input wire cin,
output wire sum,
output wire cout
);
assign {cout, sum} = a + b + cin;
endmodule
This is the same circuit again, just described at a higher level: add the three bits and let the 2-bit result split into cout (the overflow bit) and sum. On FPGA targets that provide dedicated fast-carry hardware, describing addition this way, rather than as discrete gates, gives the synthesis tool the clearest signal to use it. Whether that hardware is available and how it is used depends on the specific FPGA family; check your target device’s synthesis documentation rather than assuming, since this is not something a beginner needs to verify to get correct, working logic from any of the three styles above.
Testing It in Simulation First
A testbench that exercises all eight rows of the truth table confirms the module before it ever touches hardware:
module full_adder_tb;
reg a, b, cin;
wire sum, cout;
full_adder_behavioral uut (
.a(a), .b(b), .cin(cin),
.sum(sum), .cout(cout)
);
initial begin
$monitor("a=%b b=%b cin=%b -> sum=%b cout=%b", a, b, cin, sum, cout);
a = 0; b = 0; cin = 0; #10;
a = 0; b = 0; cin = 1; #10;
a = 0; b = 1; cin = 0; #10;
a = 0; b = 1; cin = 1; #10;
a = 1; b = 0; cin = 0; #10;
a = 1; b = 0; cin = 1; #10;
a = 1; b = 1; cin = 0; #10;
a = 1; b = 1; cin = 1; #10;
$finish;
end
endmodule
Run this and check the $monitor output against the truth table above, row by row. All eight combinations matching confirms the logic before you move to hardware, which is the same discipline covered for the D flip-flop: simulation catches logic mistakes, hardware catches everything simulation cannot. Note that $monitor and this entire testbench module are simulation-only constructs, run in a simulator such as Icarus Verilog, not synthesizable circuits: none of it gets built into real gates on the FPGA. Only the full_adder_structural, full_adder_behavioral, or full_adder_arithmetic modules above get synthesized; the testbench exists purely to verify them before hardware.
From Simulation to Real Hardware
Because a full adder is combinational, there is no clock signal to wire up, which makes it a genuinely simpler first hardware exercise than the flip-flop circuits earlier in this guide. On an EIM STEPFPGA board, assign a, b, and cin to three physical switches and sum and cout to two LEDs, and every one of the eight rows in the truth table becomes something you can verify by hand, flipping switches and watching the LEDs respond immediately, with no clock edge to wait for.
This circuit does not need the debounce logic covered in the flip-flop exercises, but the reason is narrower than “combinational circuits do not need debouncing,” so it is worth getting precise. A bouncing switch still produces rapid, high-frequency glitches on a combinational output; that does not go away just because there is no clock. What changes is the consequence. A flip-flop samples its input at one specific clock edge, so if a bounce happens to land on that instant, the flip-flop captures the wrong value and holds it, a real, incorrect, and persistent state. A full adder has no sampling instant and no memory: the glitches ripple through and disappear well within microseconds, faster than an LED or a human eye can register, and the very next stable input state is what you actually see. That is fine for the LED demo in this guide. It stops being fine the moment this circuit’s output feeds something with a clock, a register, or an interrupt further down the design, because at that point the same brief glitch can be sampled and captured as a real error. Treat “no debounce needed” as true for this specific combinational, LED-only exercise, not as a general rule for every circuit you build afterward.
The FPGA Learning Kit walks through exactly this build as one of its early exercises, precisely because a combinational circuit like this is the right complexity level once you have the flip-flop fundamentals down.
Where This Goes Next
You have now built both halves of digital design’s foundation: memory, from the flip-flops guide, and arithmetic, here. The natural next step combines a variant of this circuit with a display: see Seven Segment Displays for how to take a binary value, like the output of a chain of full adders, and actually show it as a human-readable digit.
For the complete sequence of what to build and in what order, see FPGA Projects for Beginners. If you have not yet decided which language to commit to, Verilog or VHDL: Which Language to Learn First explains the reasoning behind using Verilog throughout this guide.
Frequently Asked Questions
What is the difference between a half adder and a full adder?
A half adder adds two single-bit inputs and produces a sum and a carry-out, but has no input for a carry-in from a previous bit. A full adder adds three inputs, the two operand bits plus a carry-in, which lets it be chained with other full adders to add numbers wider than one bit. A full adder can be built from two half adders and an OR gate.
Is a full adder a combinational or sequential circuit?
Combinational. Its outputs depend only on its current inputs, with no memory of past inputs and no clock signal involved. This is different from the flip-flops covered elsewhere in this guide, which are sequential and depend on both the current input and the circuit’s stored state.
How many half adders are needed to build a full adder?
Two, plus one OR gate. The first half adder combines the two operand bits (A and B). The second half adder combines that result with the carry-in (Cin). The final carry-out is the OR of the two half adders’ carry outputs.
What are full adders used for?
Chaining multiple full adders together, with each one’s carry-out feeding the next one’s carry-in, builds a multi-bit adder capable of adding numbers of any width. This ripple carry adder structure, or faster variants of it, is the arithmetic core inside counters, arithmetic logic units, and any FPGA design that needs to add binary numbers.
What is a full adder circuit diagram made of?
At the gate level, a full adder is typically drawn as two XOR gates, two AND gates, and one OR gate, arranged to match the two-half-adder structure: one XOR and one AND per half adder, plus the final OR combining the two carry outputs. The Verilog structural example in this guide mirrors that same gate arrangement directly.
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Daniel Cao is the Founder of EIM Technology and holds a Master of Applied Science in Engineering. With experience in engineering research, product development, PCB design, and technical education, he is the author of several books on electronics engineering. His work focuses on developing practical learning systems that integrate engineering hardware, lab instruments, curriculum, and project-based learning. Through EIM Technology, Daniel aims to make electronics and computer engineering more accessible and engaging, helping students build real experience in designing, measuring, testing, and troubleshooting electronic systems.
